36. Metastability and Clock Skew Issues

Two critical, real-world problems plague high-speed sequential design: metastability and clock skew.

1. Metastability

Metastability occurs when the setup or hold time requirements are violated (usually because an input changes exactly at the clock edge). The flip-flop enters an unstable state where its output Q is neither a clear 0 nor a clear 1.

• Consequence: The FF may eventually settle to 0 or 1, but the time taken is unpredictable. If this settling time exceeds the clock period, the system fails.
• Solution: Primarily addressed by using synchronizers (cascaded FFs) when interfacing between asynchronous and synchronous domains.

2. Clock Skew

Clock skew is the difference in arrival time of the clock signal at different flip-flops within the same circuit. Due to physical wiring differences, the clock edge may arrive at FF1 slightly earlier or later than at FF2.

• Consequence: A positive clock skew can effectively reduce the effective hold time for data transferred between FFs, potentially causing hold time violations and system failure.
• Solution: Careful layout and design of the clock distribution network (using buffers and clock trees).