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Basic Data Register Design (Parallel Load)

Digital Logic Systems: From Zero to Hero

38. Basic Data Register Design (Parallel Load)

We will design a simple 4-bit register with a parallel load capability.

Components

  1. Four D Flip-Flops ($FF_0$ to $FF_3$).
  2. A common Clock (CLK) input.
  3. A Load/Enable control signal (L).

Implementation Detail

We need to ensure that when $L=0$, the input to each D FF is its own current output ($Q_i$), and when $L=1$, the input is the external data ($D_i$). This selection is performed using a 2-to-1 Multiplexer for each bit.

Logic for $FF_i$ Input ($D_{FF, i}$):

$$D_{FF, i} = \overline{L} Q_i + L D_i$$

  • When $L=1$, $D_{FF, i} = D_i$ (Load new data).
  • When $L=0$, $D_{FF, i} = Q_i$ (Hold current data).

On the next clock edge, the value stored in $D_{FF, i}$ is transferred to $Q_i$. This mechanism allows the register to store data indefinitely until a new load signal is asserted.