Back to course

Ripple Carry Adders (N-bit Parallel Adders)

Digital Logic Systems: From Zero to Hero

21. Ripple Carry Adders (N-bit Parallel Adders)

To add two N-bit numbers, we connect N Full Adders in a chain, forming an N-bit parallel adder.

Structure

  1. The least significant bit (LSB) stage uses a Full Adder where the initial carry-in ($C_{in, 0}$) is usually set to 0.
  2. The $C_{out}$ from one stage is connected directly to the $C_{in}$ of the next, more significant stage.

This structure is called a Ripple Carry Adder because the carry signal 'ripples' or propagates through the stages sequentially, from LSB to MSB.

Performance Limitation: Critical Path

The total time required for the addition operation is determined by the time it takes for the carry signal to ripple through the entire chain of N adders. This path is known as the critical path.

$$\text{Total Delay} = N \times t_{\text{carry}}$$ (where $t_{\text{carry}}$ is the delay of the carry computation within one FA).

For large N (e.g., 64-bit CPU), this delay can become significant, slowing down the processor clock speed. This leads to the need for faster adder designs, like the Lookahead Carry Adder (introduced conceptually later).