31. Flip-Flops: SR Flip-Flop (Edge-Triggered)
Flip-Flops (FFs) are the fundamental storage elements in synchronous systems. They are constructed by adding clock control logic to a basic latch, typically using a master-slave configuration or dedicated edge-detection circuitry.
SR Flip-Flop Structure
The clocked SR Flip-Flop adds a Clock (CLK) input and uses logic gates to ensure that the S and R inputs are only transferred to the internal latch when the clock is active (or specifically, when the clock edge occurs).
Characteristic Table (Positive Edge Triggered)
$Q(t+1)$ represents the next state, $Q(t)$ represents the current state.
| S | R | CLK | Q(t+1) | Operation |
|---|---|---|---|---|
| X | X | 0 or 1 Level | Q(t) | Hold (No Edge) |
| 0 | 0 | $\uparrow$ | Q(t) | Hold |
| 0 | 1 | $\uparrow$ | 0 | Reset |
| 1 | 0 | $\uparrow$ | 1 | Set |
| 1 | 1 | $\uparrow$ | X | Invalid |
Difference from Latch
The FF is immune to input changes while the clock is inactive or stable. It only captures the input values present exactly at the rising (or falling) edge of the clock signal. This isolation is essential for building complex sequential systems like counters and memory banks.