29. Latches: The Unclocked SR Latch
A latch is the simplest form of a memory element. It is level-sensitive, meaning its state can change as long as its enable signal (if present) is active.
The SR Latch (Set-Reset)
We typically build an SR Latch using cross-coupled NOR gates or NAND gates.
NOR Gate Implementation
- Inputs: S (Set), R (Reset).
- Outputs: Q (Normal state), $\overline{Q}$ (Complement state).
| S | R | Q (Next State) | Operation |
|---|---|---|---|
| 0 | 0 | Previous Q | Hold/Memory |
| 0 | 1 | 0 | Reset |
| 1 | 0 | 1 | Set |
| 1 | 1 | X | Invalid (Race Condition) |
The Hold State
When $S=0$ and $R=0$, the output Q holds its previous value. This demonstrates the circuit's memory capability.
The Invalid State (S=1, R=1)
In the NOR Latch, when $S=1$ and $R=1$, both Q and $\overline{Q}$ try to go to 0. If S and R return to 0 simultaneously, the final state of Q is unpredictable (a race condition). This state must be avoided in design.